Formaler Nachweis der Fehlertoleranz von Schaltkreisen

While facing continuously shrinking feature sizes, the demand for fault tolerance in digital circuits increases. Numerous approaches to achieve such robustness on the design side have been presented. But ensuring that the fault tolerance is really achieved is a tough verification problem. Here, we propose a formal model and an effective algorithm to formally prove the robustness of a digital circuit. The proposed model uses a fixed bound in time to cope with the complexity of the sequential equivalence check. The result is a lower and upper bound of the robustness. The underlying algorithm and techniques to improve the efficiency are presented. In the experiments the efficiency was evaluated on circuits with different fault detection mechanisms.